Embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional (3-D) nonvolatile memory device including a pipe gate, a memory system including the 3-D nonvolatile memory device, and a method of manufacturing the 3-D nonvolatile memory device.
A nonvolatile memory device retains data stored therein although the supply of power is cut off. As the recent improvement of the degree of integration of 2-D memory devices in which memory cells are formed in a single layer over a silicon substrate reaches the limit, there is proposed a 3-D nonvolatile memory device in which memory cells are vertically stacked in multiple layers from a silicon substrate.
The structure of a known 3-D nonvolatile memory device and problems thereof are described in detail below.
FIG. 1 is a perspective view showing the structure of a conventional 3-D nonvolatile memory device. Interlayer insulating layers are not shown in FIG. 1, for convenience of description.
As shown in FIG. 1, the conventional 3-D nonvolatile memory device includes a channel CH. The channel CH includes a pipe channel layer P_CH buried in a pipe gate PG and a pair of memory channel layers M_CH coupled to the pipe channel layer P_CH. The channel CH is surrounded by a tunnel insulating layer, a charge trap layer, and a charge blocking layer (not shown).
The 3-D nonvolatile memory device further includes word lines WL stacked to surround the memory channel layers M_CH and a source select line SSL and a drain select line DSL which are disposed over the word lines WL.
Strings that are adjacent to each other in a second direction II-II′ are coupled to one source line SL in common, and the strings included in a string column extended in the second direction II-II′ are coupled to a common bit lines BL.
In accordance with the above structure, the tunnel insulating layer, the charge trap layer, and the charge blocking layer that surround the pipe channel layer P_CH function as the gate insulating layer of the pipe gate. However, the tunnel insulating layer, the charge trap layer, and the charge blocking layer do not have a sufficient thickness for the gate insulating layer. Consequently, there is a problem in that the threshold voltage of the pipe gate rises due to the back tunneling of electrons when an erase operation is performed or the threshold voltages of memory cells are shifted by read disturbance.